1. Field
Example embodiments relate to a method and system of analyzing a failure in a semiconductor integrated circuit device.
2. Description of the Related Art
A variety of conventional failure analyzing techniques are available, including, for example, a defect inspecting method, a physical analysis method, an electrical characteristic measuring method, etc. In the defect inspecting method, the external appearance of a wafer is inspected whenever each of a plurality of production processes is performed, and the position and size of a defect are inspected. In the physical analysis method, a defect of a wafer is directly detected by physically deprocessing the wafer after completely processing the wafer. In the electrical characteristic measuring method, the position of a fail bit is detected and a yield, e.g., a proportion of good chips among all the chips (or dies), is detected by measuring the electrical characteristics of SRAM cells after completing a wafer fabrication process.
However, these conventional failure analyzing techniques are difficult to perform on a large scale and are time-consuming. In addition, the defect inspecting method involves performing inspection whenever each of a plurality of production processes is performed, which may increase a manufacturing time and labor cost, ultimately increasing the cost of semiconductor chips. Furthermore, as design rules gradually decrease and semiconductor processes become more complicated, it is not possible to achieve satisfactory failure analysis results simply by performing the electrical characteristic measuring method.